The present invention generally relates to a viterbi equalizer which eliminates intersymbol interference which may take place in a data reproduction system of a recording/reproducing device, such as a magnetic disk device. Further, the present invention is concerned with a recording/reproducing device using such a viterbi equalizer.
Recently, there has been considerable activity in the development of small-size, large capacity magnetic disk devices. It is known that, as the storage density on a magnetic disk increases, the distance between two adjacent recorded bits decreases. More specifically, as shown in FIG. 1, recorded bits b1 and b2 are adjacent to each other in the radial direction of the magnetic disk, and recorded bits b1 and b3 are adjacent to each other in the same direction. A read head 72 is positioned immediately above the bit b1. In this state, the read head 72 receives leakage fluxes resulting from the bits b2 and b3. Thus, a reproduction (read) current output by the read head 72 is affected by intersymbol interference.
FIG. 2 is an equivalent circuit of the transfer function of a recording/reproducing model of the above-mentioned high recording density magnetic disk device. A recording current (write data) input to a write head 71 shown in FIG. 1 is sequentially applied to delay elements 81 and 82 connected in series. Multipliers 83, 84 and 85 multiply the recording currents of different timings by multiplication coefficients G0, G1 and G2, respectively. An adder 86 adds output signals of the multipliers 83, 84 and 85, and outputs the reproduction current (read data).
It will be noted that the recording/reproducing model shown in FIG. 2 is a convolutional encoder. Thus, it is possible to decode the reproduction current output by the recording/reproducing model by means of a viterbi decoder, so that the intersymbol interference can be eliminated using an error correction function of the viterbi decoder (see U.S. Pat. No. 4,763,328, the disclosure of which is hereby incorporated by reference).
FIG. 3 shows a magnetic disk device using a conventional viterbi equalizer. Recording (write) data is written into a recording/reproducing system 12, which outputs a reproduction (read) current. This reproduction current is converted into a digital signal by an analog-to-digital (A/D) converter 13. The digital signal is input to a viterbi equalizer 17, which eliminates an intersymbol interference and outputs reproduction data. A clock extracter 15 extracts a timing clock from the recording/reproducing system 12. The extracted timing signal is applied to the A/D converter 13 and the viterbi equalizer 17.
FIG. 4 is a trellis state transition diagram of a viterbi equalizer configured with the constraint length equal to 3. It will be noted that 0 and 1 of the internal state of each node correspond to -1 and +1 of the reproduction current, respectively, and there are four states (-1, -1), (-1, +1), (+1, -1) and (+1, +1). A decision circuit in the viterbi equalizer which selects a maximum likelihood path is configured so that it forms the nodes and branches of the trellis state transition diagram of FIG. 4 based on the viterbi decode algorithm.
FIG. 5 shows the entire structure of such a conventional decision circuit. The reproduction current output from the read head 72 (FIG. 1) of the recording/reproducing system 12 (FIG. 3) passes through the A/D converter 13, and is then input, as a reproduction signal R, to a distributor 4 of the viterbi equalizer 17. The distributor 4 calculates a branch metric BM related to each node with respect to the digital reproduction signal R obtained at the present time. In the distributor 4 shown in FIG. 5, the branch metric BM is defined by calculating the Euclidean distance. Instead of the Euclidean distance, it is possible to use an alternative code distance, such as the Hamming distance. The branch metrics BM calculated by the distributor 4 are input to an ACS (Adder, Comparator and Selector) circuit 5.
The ACS circuit 5 is comprised of four ACS units 51-54 respectively corresponding to the four nodes. The ACS units 51-54 each include adders (ADD), a comparator (COMP) and a selector (SEL), and are connected so that the trellis state transition diagram of FIG. 4 can be formed. Each of the ACS units 51-54 adds the current branch metric BM calculated by the distributor 4 and a path metric which is related to the immediately previous timing (via the feedback path) and which is calculated by the ACS circuit 5, and calculates two current path metrics PM of the two paths on the input side of the corresponding node. The comparator COMP of each of the ACS units 51-54 compares the two path metrics with each other, and instructs the selector SEL to select, as a surviving path, one of the two paths which has a path metric smaller than that of the other path. The path metric related to the selected surviving path is fed back to the input side of each of the ACS units 51-54. Path select signals PS-1, PS-2, PS-3 and PS-4 used for respectively selecting the surviving paths in the ACS units 51-54 are input to a path memory 6. The path memory 6 convolutionally generates and records the locus of a maximum likelihood path based on the path select signals PS-1 through PS-4.
FIG. 6 is a block diagram of the path memory 6 shown in FIG. 5. The path memory 6 has a plurality of unit circuits, each having a selector SEL and a flip-flop FF, the latter serving as a latch circuit. The unit circuits are arranged so that the trellis state transition diagram of FIG. 4 is formed. Each selector SEL is controlled by one of the path select signals PS-1 through PS-4.
In conventional viterbi equalizers as mentioned above, it is necessary to use a long constraint length in order to precisely perform the equalization. As the constraint length increases, the number of internal states, that is, the number of nodes increases exponentially, and thus the hardware scale increases exponentially. If the precise equalization is implemented by software, the number of steps of the maximum likelihood path determination program increases exponentially as the constraint length increases.